The present invention relates to solid-state image sensors, specifically to charge detection nodes of image sensors that employ feedback directly to the node to dynamically vary conversion gain.
A typical image sensor senses light by converting impinging photons into electrons that are integrated (collected) in sensor pixels. After completion of integration cycle charge is converted into a voltage that is supplied to the output terminals of the sensor. The charge to voltage conversion is accomplished either directly in the sensor pixels, such as in the Active Pixel CMOS image sensors, or remotely, off the sensing area, in charge conversion amplifiers. The key element of every charge conversion amplifier is the charge detection node. As charge is transferred onto the node the node potential changes in proportion to the amount of transferred charge and this represents signal. The charge detection node is typically connected to a gate of a suitable MOS transistor that serves as a first stage of the amplifier. The charge detection node is also provided with reset transistor that removes charge from the node after sensing.
There are many charge detection node and amplifier designs known in the literature. The most popular structure is the Floating Diffusion (FD) architecture. The detail description of such systems can be found, for example, in the book: xe2x80x9cSolid-State Imaging with Charge-Coupled Devicesxe2x80x9d by Albert J. P. Theuwissen pp. 76-79 that was published in 1995 by Kluwer Academic Publishers.
This patent deals with the FD type of charge detection node and describes improvements to the basic concept.
The performance of any charge detection system can be evaluated according to the following main criteria: the charge conversion factor, the dynamic range, noise floor, reset feed-through, and linearity. The charge conversion factor is determined by the overall detection node capacitance that also includes the node parasitic capacitances. It is thus desirable to minimize the parasitic capacitances and maximize the charge conversion factor. The dynamic range (DR) of the node is determined by the ratio of the maximum signal handling amplitude to the noise floor. It is desirable to minimize the noise floor in order to maximize the DR. The FD charge detection node has to be reset after sensing of charge. The reset is typically accomplished by turning on a reset transistor that is connected to the node. The reset transistor, however, causes reset noise. Reset noise needs to be reduced and this is typically accomplished by using a special signal processing method, somewhere downstream in the system, as is well known to those skilled in the art. Reset noise increases the detection node noise floor and therefore reduces DR. It is desirable to reduce reset noise right at the detection node itself rather than downstream in the signal processing chain. Another difficulty, typically encountered in standard charge detection node designs, is the problem of limited DR. It is desirable to have a large conversion gain in order to detect small amounts of charge. The large conversion gain also leads to smaller reset noise. However, it is also desirable to detect large signals with the same detection node particularly in the CCDs that use Charge Multipliers. To detect large amounts of charge the detection node must have a smaller conversion gain, therefore larger capacitance, and thus higher noise floor. These are contradictory requirements that cannot be satisfied at the same time. In practice it is difficult to find a good compromise with the current state of the art detection node designs that cannot dynamically vary conversion gain and that have reset noise eliminated elsewhere in the system.
It is an object of the present invention to overcome limitations in the prior art. It is a further object of the present invention to provide a practical FD charge detection node design that minimizes reset noise directly at the detection node itself, which results in a low noise floor and a high DR. It is yet another object of the present invention to provide a practical high performance charge detection node design where the conversion gain may be varied. Finally, it is the object of the present invention to provide the FD charge detection node design that has high DR, good linearity, and a dynamically variable charge conversion gain where the gain is varied according to the expected signal in a programmable fashion using a DSP.
Incorporating a feedback system directly into the charge detection node that uses a variable gain amplifier, which may be controlled by a suitable DSP, achieves these and other objects of the invention.